On-Chip Memory System & Hardware support of Data Structure

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The electronic forum deals with the topics related to analog and digital circuits and systems (i.e. ASIC, FPGA, DSPs, Microcontroller, Single/Multi Processors, PCBs etc) and their programming such as HDL, C/C++, etc.

On-Chip Memory System & Hardware support of Data Structure

Unread postby UCERD.COM » Sat Jul 27, 2013 4:44 am

Abstract— Many data intensive High Performance Computing (HPC) applications may present irregular data structures, irregular control flow and irregular memory accesses.
Current HPC memory systems are designed access regular data, accessing irregular data structures require multiple read/write memory
accesses which affects the performance of the system.
In this paper, we proposed integration of linear and non-linear data structure support in a memory controller called Programmable Memory Controller PPMC.

Related Work
On-chip MRAM as a High-Bandwidth,Low-Latency Replacement for DRAM Physical Memories

Memory Access Pattern Analysis and Stream Cache Design for Multimedia Applications

Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
Attachments
memories.pdf
(50 KiB) Downloaded 116 times
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